The present invention relates to a method of testing semiconductor integrated circuits whereby a plurality of semiconductor integrated circuit elements (semiconductor chips) are tested simultaneously for electric characteristics and to a testing board for use in the testing method.
In the process of fabricating a conventional semiconductor integrated circuit device, an electrical connection is provided between a semiconductor chip and a leadframe by a bonding wire and then the semiconductor chip and the leads of the leadframe are sealed with a resin or ceramic to be mounted on a printed circuit board.
To meet the demand for an electronic device reduced in both size and price, there has been developed a method of mounting, on a circuit board, a semiconductor integrated circuit device as a bare chip cut out of a semiconductor wafer. The bare chip used in the method is preferably a quality-assured bare chip supplied at lower price. For the quality assurance of a bare chip, it is preferable, in terms of cost reduction, to perform a simultaneous burn-in process with respect to a plurality of semiconductor chips formed in a single semiconductor wafer.
In accordance with a known testing method, a simultaneous burn-in process is performed with respect to a plurality of semiconductor chips formed in a semiconductor wafer by using a contactor having probe terminals to be connected to the respective testing electrodes of the semiconductor chips. In this case, it is required to apply power-source voltage or ground voltage to the testing electrode of each of the semiconductor chips. For individual application of the power-source voltage or ground voltage to the testing electrodes of the semiconductor chips, however, a large number of wires should be routed over the contactor or semiconductor wafer, which is not realistic.
To overcome the drawback of the method, there has been proposed another method wherein a common power-source-voltage supply line or ground-voltage supply line (hereinafter generally referred to as common voltage supply lines) is provided such that power-source voltage or ground voltage is applied to each of the testing electrodes therethrough, thus avoiding the necessity for routing a large number of wires.
However, the provision of such common voltage supply lines on the contactor or semiconductor wafer is disadvantageous in that, if a defective semiconductor chip electrically short-circuited exists in the semiconductor wafer, the common power-source-voltage supply line and the common ground-voltage supply line are short-circuited via the defective semiconductor chip.
To eliminate the disadvantage, U.S. pat. application Ser. No. 08/358609 (Japanese Unexamined Patent Publication No. 7-169806) has proposed a method of testing semiconductor integrated circuits wherein the individual semiconductor chips are preliminarily tested for electric characteristics before a burn-in process is performed thereto and the semiconductor chip judged to be defective in the preliminary test is coated with a liquid insulating agent. The liquid insulating agent is then cured to form a non-conductive layer over the testing electrode of the defective semiconductor chip, thereby preventing a current flow through the defective semiconductor chip. After that, a simultaneous burn-in process is performed with respect to the other conforming semiconductor chips.
Although the conventional method of testing semiconductor integrated circuits can screen out the semiconductor chip judged to be defective in the preliminary electric characteristic test before the burn-in process, it is still disadvantageous in that, if a defective semiconductor chip is produced for some reason during the burn-in process, the burn-in process cannot be performed with respect to the other conforming semiconductor chips.
For example, there are cases where some disturbance causes a latch-up phenomenon in a CMOS integrated circuit during the burn-in process so that an abnormal current flows through the CMOS integrated circuit having undergone the latch-up phenomenon. Since a large current flows between the common power-source voltage line and the common ground voltage line via the semiconductor chip having undergone the latch-up phenomenon, the burn-in process cannot be performed with respect to the other semiconductor chips.
Moreover, since wiring is more complicated and the density of a current flowing through the wiring is higher in a semiconductor integrated circuit becoming denser and increasingly miniaturized, the current density excessively increased by some disturbance in the burn-in process may cause an electromigration, which leads to a short circuit in the wiring. In this case also, a large current flows between the common power-source voltage line and the common ground voltage line via the semiconductor chip having undergone the electromigration and the burn-in process cannot also be performed with respect to the other semiconductor chips.
If a defective semiconductor chip is produced during the burn-in process for some reason and an extraordinarily large quantity of current flows through the defective semiconductor chip, the temperature of the defective semiconductor chip is increased to a high degree so that another conforming semiconductor chip adjacent to the defective semiconductor chip is also heated to a high temperature, resulting in abnormal operation. Thus, even when the defective semiconductor chip and the conforming semiconductor chip are not connected to the common voltage supply line, the burn-in process cannot be performed with respect to the conforming semiconductor chip as long as they are formed in a single wafer.
To circumvent the occurrence of a reversible short circuit such as the latch-up phenomenon and an irreversible short circuit in one semiconductor chip, which prevents the application of a voltage from the common voltage supply line to another semiconductor chip or the testing of the electric characteristics of a conforming semiconductor chip formed adjacent to a defective semiconductor chip abnormally heated on a single semiconductor wafer, a fuse may be interposed between the voltage supply line and the testing electrode of the semiconductor chip, thereby electrically disconnecting the defective semiconductor chip from the voltage supply line.
However, the fuse interposed between the voltage supply line and the testing electrode presents the problems that, once a defective semiconductor chip is produced, the fuse melts and needs replacing and that, once an irreversible short circuit such as the latch-up phenomenon occurs, the electric characteristics cannot be tested even when the irreversible short circuit is eliminated.